Efforts to continually decrease the size of transistors and/or other semiconductor devices introduce challenges when integrating devices with different power handling capabilities on a common die. For example, memory devices may include a number of relatively low power semiconductor devices for storing data while also including relatively higher power semiconductor devices that support the various read, write, and erase operations. As device geometries decrease to enable smaller or more densely distributed lower power devices for increased storage capabilities, the power handling capabilities of the higher power semiconductor devices also decrease without modifications to the fabrication process or the device structure to compensate for the decreased device geometries. However, such modifications often undesirably increase the cost or complexity of the fabrication process, or otherwise compromise performance in an unintended manner. Thus, what is needed is a simple and cost effective means for maintaining power handling capabilities of higher power devices without sacrificing performance as device geometries decrease.